Decision Feedback Equalization (“DFE”) may be used to combat inter-symbol interference (“ISI”). DFE circuitry may thus be used in high speed serial links to improve bit error rate (“BER”), such as in a receiver of a serializer-deserializer (“SERDES”) for example. However, because of delay due to feedback in DFE, this delay may limit frequency of operation of a receiver. Therefore, adding any additional delay in a DFE path may further limit performance. For a wide-band serial link, this timing problem in DFE circuitry may be exacerbated due to a “set-up time” parameter for a high or the highest data rate that may not simultaneously satisfy a “hold-time” parameter for a low or the lowest data rate.
Accordingly, it would be desirable and useful to provide a receiver with DFE that may be used for both high and low data rates which overcomes the above-described limitation without having to introduce additional delay in a DFE path.